The Assignee of the present application has developed a platform ASIC technology called RAPIDCHIP that lets designers quickly and affordably create high-performance, complex, customized ICs. A platform ASIC is a chip building technique where a reference design, referred to as a slice, serves as a starting point for the design of custom chips. Each platform ASIC slice is a pre-manufactured, pre-verified chip with the density and power near that of an ASIC in which all silicon-based layers have been built, leaving the top metal layers to be completed with the customer's unique intellectual property. The customer selects a desired slice that best accommodates their application, and then uses a software tool suite to create a proprietary design, called an instance, using the gates on the final metal layers of the chip to pattern interconnect for gates and memories that embody the customers design. The result is a completed chip with near ASIC performance and density, done in the time it takes to do an FPGA, yet at much lower unit cost.
The platform ASIC procedure includes the following steps. First, an IC manufacturer provides one or more pre-built slices, and then a customer creates a custom design by selecting what components of the slice will be used in the instance. The custom design is then handed-off to the IC manufacturer who completes manufacturing of the slice by adding the customer defined top layers of metal. The customer designs a printed circuit board (PCB) on which the platform ASIC instance will be mounted. Both the platform ASIC and PCB are then manufactured and tested prior to shipment.
One problem with this procedure is that it would be desirable to perform system functional testing, including the PCB, before platform ASIC samples can be prepared. Performing functional tests can be accelerated using Field Programmable Gate Arrays (FPGA) as a prototype for the platform ASIC. However, using FPGAs for prototyping a platform ASIC has disadvantages, which include using a different mixture of resources (e.g., I/O signaling voltages) than the platform ASIC, and having a different pin-out than the platform ASIC. Due to such footprint incompatibility, the traditional use of FPGAs for platform ASIC prototyping does not allow a customer to perform functional testing on the PCB in advance of the availability of platform ASIC prototype samples.
Accordingly, what is needed is a system and method for accelerating PCB development and debug in advance of platform ASIC prototype samples. The present invention addresses such a need.